1. Field of the Invention
The present invention relates to a compound semiconductor field effect transistor and a manufacturing process thereof in which the cap layer for contact resistance reduction has a recess structure, and more specifically, a field effect transistor and a manufacturing process thereof for achieving high breakdown voltage.
2. Description of the Related Art
In the case of a field effect transistor (FET) with a recess structure, electrons are trapped on the surface by forming the passivation film or carrying out functions as FET, and the electric field concentrated portion moves from the drain edge of the gate to the recess edge on the drain side with a sharp angle. In the field effect transistor, there are avalanche effect and tunnel current from the electric field concentrated portion for factors to determine the reverse breakdown voltage characteristics between gate and drain. Consequently, in the case of the field effect transistor with a recess structure, the reverse breakdown voltage value is restricted by the recess edge, that is, the recess profile.
FIG. 1 is a schematic cross-sectional view showing the construction of the heterostructure FET of conventional FETs which have the GaAs cap layer. In FIG. 1, on the semi-insulating GaAs substrate 171, undoped GaAs buffer layer 172, undoped Al.sub.0.3 Ga.sub.0.7 As heterostructure buffer layer 173, undoped GaAs channel layer 174, impurity doped Al.sub.0.3 Ga.sub.0.7 As donor layer 175, and impurity doped GaAs contact resistance reducing cap layer 176 are laminated successively by the epitaxial growth process. And the impurity doped GaAs contact resistance reducing cap layer 176 is shaved by recess-etching, and thereafter, a gate electrode 177 is formed on the impurity doped Al.sub.0.3 Ga.sub.0.7 As donor layer 175, and source and drain electrodes 178, 179 are formed on the cap layer 176.
FIG. 2 shows the potential distribution when voltage is applied to the conventional FET, while FIG. 3 shows the voltage resistance characteristics. In general, when the passivation film is formed, or functions as FET are being carried out, it is known that electrons are trapped on the semiconductor surface or semiconductor/passivation film interface. It is known that by this electron capture, the potential which has the surface condition liable to be influenced changes and the electric field concentrated portion moves not to the gate edge between the gate and the drain but to the drain side.
As shown in FIG. 2, the potential distribution 810 moved to the drain side is concentrated to the recess edge on the drain side with an obtuse angle or acute angle formed from the surface of the impurity doped Al.sub.0.3 Ga.sub.0.7 As donor layer 175 to which the gate electrode is arranged and the side of the impurity doped GaAs contact resistance reducing cap layer 176. Consequently, the reverse breakdown voltage value that serves as a major factor for determining the potential distribution is determined on the recess edge on the drain side.
However, since in the FET shown in FIGS. 1 through 3, the recess edge on the drain side has either an acute or obtuse profile, the electric field distribution moved to the drain side is concentrated at the recess edge with this angle. Consequently, avalanche yield occurs at this recess edge and the reverse breakdown voltage value is determined. That is, the conventional FET has a problem of restricting the breakdown voltage characteristics by the recess edge on the drain side with the angle formed from the semiconductor surface which comes in contact with the side surface of the contact resistance reducing cap layer at the gate electrode. In addition, carrying out equivalent etching at both edges of the drain side and the source side increases resistance on the source side, and as a result, FET characteristics may be degraded.